1. Field of the Invention
The present invention relates to the field of semiconductor fabrication and more particularly forming high dielectric constant gate dielectrics for a transistor gate.
2. Discussion of Related Art
High dielectric constant (k) gate dielectric layers are valuable in scaling down the dimensions of transistors. This is because, in order to make the gate dielectric layer thinner and smaller in area while still maintaining a high capacitance for the transistor, the dielectric constant of the gate dielectric layer must be increased. A high dielectric constant material is defined as a material having a dielectric constant greater than approximately 4 (the dielectric constant of silicon dioxide). High dielectric constant materials include HfO2, Si3N4, Ta2O3, and PZT (PbZrTiO3). Ideally, a high dielectric constant material would be deposited directly onto a semiconductor substrate to form a gate dielectric layer. But, the atomic layer deposition (ALD) process that is used to deposit high dielectric constant materials, such as HfO2, onto a semiconductor substrate cannot deposit the high dielectric constant materials directly onto a semiconductor substrate, such as silicon. High dielectric constant materials may be deposited by ALD onto an oxide surface, such as silicon dioxide. Therefore, by forming an oxide surface on a semiconductor substrate, the high dielectric constant material may be deposited onto the oxide surface of the semiconductor substrate. But, silicon dioxide has a relatively low dielectric constant as compared to the high dielectric constant materials such as HfO2. Silicon dioxide has a dielectric constant of approximately 4, and HfO2 has a dielectric constant of approximately 20. The overall dielectric constant of a gate dielectric formed of silicon dioxide and a high dielectric constant material will be lower than that of the high dielectric constant material alone. Therefore, the silicon dioxide layer must be as thin as possible, and ideally only as thick as a monolayer of silicon dioxide (2 angstroms) to minimize the effect that the silicon dioxide has of lowering the overall dielectric constant of the gate dielectric layer.